1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more specifically to an flash electrically erasable and programmable non-volatile semiconductor memory (flash EEPROM).
2. Description of Related Art
In the prior art, a non-volatile semiconductor memory includes a memory cell array, which is composed of a number of memory cells arranged in the form of a matrix, each of the memory cells being constituted of a floating gate field effect transistor (called a "FAMOS" hereinafter). A word line is located to extend along each of rows in the memory cell array, and a digit line is also located to extend along each of columns in the memory cell array. A row address decoder selectively activates one of the word lines, and a column address decoder also selectively activates one of the digit lines, so that one memory cell is selected. The digit lines are connected to sense amplifiers, so that the on/off condition of the selected memory cell is detected.
Here, the off condition of the memory cell can be set by a writing operation, by which electrons are injected into the floating gate of the FAMOS, so that a threshold voltage is elevated. On the other hand, the on condition of the memory cell is realized-by an erasing operation for extracting the electrons stored in the floating gate of the FAMOS, so that the threshold voltage is lowered.
With the erasing operation of the non-volatile semiconductor memory, a plurality of memory cells are simultaneously erased in the flash memory. In this flash erasing operation, the potential of the source region of the FAMOSs are put to a high voltage during a predetermined constant period of time. With application of the high voltage to the source region of the FAMOSs, the electrons stored in the floating gate are extracted by a Fowler-Nordheim tunneling phenomenon, resulting in drop of the threshold voltage of the FAMOS.
Referring to FIG. 1, there is shown one example of an erase circuit used in a conventional non-volatile semiconductor memory.
As shown in FIG. 1, the erase circuit 2 receives an erase signal ER and drives a memory cell common source line VS, which is connected to a source electrode of FAMOS memory cells M00 to Mnm in a memory cell array 1. More specifically, the erase circuit 2 includes a pair of buffers 31 and 32, each of which has an input connected to receive the erase signal ER. The buffer 32 is configured to output a signal having an amplitude reaching a Vpp level. An output ER0 of the buffer 31 is connected to a gate of an N-channel MOS transistor MN0, which has a source connected to ground and a drain connected to the common source line VS. An output ER0 (Vpp) of the buffer 32 is connected to a gate of a P-channel MOS transistor MP0, which has a source connected to an erasing voltage Vpp and a drain connected to the common source line VS.
Now, operation of the erase circuit shown in FIG. 1 will be described. In a condition other than the erasing operation, the erase signal ER is maintained at a high level. Therefore, the P-channel transistor MP0 is off and the N-channel transistor MN0 is on, so that the common source line VS is driven to the ground level.
In the erasing operation, the erase signal ER is brought to a low level, so that the N-channel transistor MN0 is turned off and the P-channel transistor MP0 is turned on. Thus, the common source line VS is driven toward the erasing voltage Vpp, so that the source region of each FAMOS memory cell is brought to the high voltage, and the erasing operation of the memory cells starts for the purpose of causing the electrons stored in the floating gate to be extracted to the source region.
It is known to persons skilled in the art that, in this source erasing method, a depletion layer is generated in the source region of the memory cell, because of a potential difference between the source region and the floating gate of the memory cell, with the result that there occurs a leakage current flowing from the source region of the memory cell to the substrate due to an inter-band tunneling phenomenon. The larger the potential difference between the source region and the floating gate of the memory cell is, the larger the leakage current flowing from the source region of the memory cell to the substrate becomes. In other words, the more the electrons stored in the floating gate is, namely, the higher the threshold value of the memory cell to be erased is, the larger the leakage current flowing from the source region of the memory cell to the substrate becomes.
Therefore, in the source erase type of flash EEPROM, the leakage current flowing from the source region of the memory cell to the substrate is large at an initial stage of the erasing operation, and lowers with the drop of the memory cell threshold voltage in accordance with the advance of the erasing. Accordingly, in the conventional erase circuit for driving the memory cell common source line with a high voltage, the P-channel MOS transistor MP0 shown in FIG. 1 has been constructed to have a small current supplying capacity, for the purpose of reducing the leakage current flowing from the source region of the memory cell to the substrate at an initial stage of the erasing operation.
Referring to FIG. 2, there is shown a characteristics diagram illustrating a relation between the memory cell common source line voltage and the leakage current flowing from the source region of the memory cell to the substrate. In the diagram shown in FIG. 2, the current supplying capacity of the P-channel MOS transistor MP0 is shown by a load line. The operating point moves along the load line with advance of the erasing operation, so that the leakage current flowing from the source region of the memory cell to the substrate and the memory cell common source line voltage change with advance of the erasing operation.
As seen from FIG. 2, when the leakage current flowing from the source region of the memory cell to the substrate changes with advance of the erasing operation, the memory cell common source line voltage elevates along the load line, and the driving current becomes smaller than a current value set by the initial stage of the erasing operation, with the result that the potential difference between the source region and the floating gate of the memory cell becomes insufficient or short, and therefore, the erasing time becomes long.
However, the prior art cannot solve this problem while making a possible solving means compatible with a request lowering the erasing power supply voltage, ceaselessly made by users.